The present invention relates to efficient addressing of large memories in a computer system, and more particularly to a simplified addressing mechanism which permits a memory device to have fewer address pins than there are address bits required to address the corresponding memory space, and even more particularly to such a memory that is also capable of providing the contents of a location alternatively from a next sequential address, or from an address specified by a processor.
In modern technology, the use of microprocessors in battery-operated portable applications has become widespread. Examples of such technology include the use of microprocessors in lap-top computers, and in embedded applications such as cellular phones. The word "embedded" is here used to distinguish applications in which the existence of a microprocessor in the product is a matter of design choice and not primary to the product's function, from those applications in which the existence of a processor is primary to the product's functions. Both of the above technological environments are characterized by small size, cost and limited battery consumption requirements, coupled with increasing complexity, and consequent increasing size, in the computer programs for controlling the devices. The push for increasingly complex computer programs in portable applications results from the desire to provide more features, coupled with the economic feasibility of using larger and larger program memories resulting from the continuing decline in the cost of such memories.
Typical microprocessors used in today's battery operated devices include the INTEL 8051, HITACHI 6303 and ZILOG Z80. These processors are often used as the main control processors in cellular phones and other embedded applications. Applications where the existence of a processor is primary to the product's functions are exemplified by personal computer (PC) or lap-top computer products. The most common microprocessors found in these applications are the INTEL 8088/8086 and its family of enhancements and the MOTOROLA 68000.
The 8051, 6303 and Z80 microprocessors have 8-bit wide data buses and 16-bit wide address buses. A 16-bit wide address bus provides the capability of selecting any one of 2 to the power 16 (=65,536) 8-bit bytes. The usual connection of such a processor to memory chips is illustrated in FIG. 1, in which a Z80 processor 10 is connected to a random access memory (RAM) 11 as well as to a read only memory (ROM) 12. In this application, the RAM 11 is used for storing program data (i.e., operands), and the ROM 12 is used for storing program instructions. The two memory chips are attached to the same bus, but the response of one or the other to an address is determined by activation of one of the Chip Select signals CS1 and CS0. CS1 is activated to enable the RAM 11 chip only if the address is, for example, in the top 16k of the 64k byte address space. In this example, CS0 is activated to enable the ROM 12 chip only if the address is in the other 48 kbytes. The ROM 12 chip could very likely be capable of responding to addresses in the top 16k range also, if it is a full 64k byte chip, and thus must be prevented from doing so and interfering with RAM reads.
When the above microprocessor architectures were conceived, the implementation of a 64k byte memory, which was thought at the time to be a large memory, required several silicon chips. By contrast, 64 kbytes of ROM are now readily available in a single chip, and a 32 kbyte RAM is considered a small chip.
A typical embedded application, such as a cellular phone controller, can comprise a fixed ROM program representing perhaps 75% of the 64k byte memory space with the remaining 25% of the address space being allocated to RAM for storing and retrieving dynamically varying quantities. Memory technology has moved on and 512 kbytes of program ROM can now be obtained on a single chip. This program storage capacity has been absorbed in the more complex, modern, digital cellular phones, such as in the pan-European Global System for Mobile communication (GSM), as part of the technical means to increase capacity for more conversations. The need for RAM storage has not increased as much, and represents perhaps only 5% of the total memory address space.
PC applications are distinguished by the need to be able to run any program the user chooses, and not just a fixed program, so virtually all memory is both readable and re-writable (i.e. RAM). Nevertheless, at any given instant during the running of a computer program, a region of this RAM is loaded with program instructions which do not change during program execution (i.e., this portion of RAM is used in a read only mode) while other regions of the RAM are used for both reading and writing of dynamically changing variables. It is possible for a program stored in RAM to dynamically alter itself, but this is considered a dubious programming trick to be used only where no good alternative exists. It is the virtue of a Von Neumann architecture that allows a program stored in data memory to be executed. This possibility is excluded in the so-called Harvard architecture (described in further detail below).
In PC applications, a 512 kbyte memory, whose address space requires a 19 bit address, is now considered barely adequate and a memory of from 4 to 16 megabytes, whose address space correspondingly requires an address ranging in size from 22 to 24 bits, is rapidly becoming the norm. Thus, as memory chips become denser and cheaper, the width of the address bus becomes increasingly larger than the width of the data bus, and dominates the chip package pin count.
The result in embedded applications, such as cellular phones, is that the goal to reduce size by retaining an 8-bit data bus is defeated by the increasing width of the address bus.
Another critical goal in these applications is the need to keep power consumption as low as possible. Energy is consumed from the battery whenever the small capacitance of input/output pins or printed circuit wiring tracks is charged or discharged by a voltage changing from the logic `1` level to the logic `0` level or vice-versa. When a 24 bit address is required for accessing an 8-bit information byte, the need to output the address from the central processing unit (CPU) to the memory can thus cost three times more power than that which is required in order to receive the information byte in return.
Prior art systems commonly place RAM (sometimes called data memory) on the same bus as ROM (sometimes called program memory). Exceptions are found in special devices known as Digital Signal Processors, such as the TEXAS INSTRUMENTS TMS320C25, which are designed to maximize processing speed and therefore provide the ability to access program memory and data memory simultaneously on two separate buses. These machines are often also of so-called Harvard architecture type, in which program and data memories constitute two separate address spaces, as distinct from Von Neumann architectures where program and data memory are parts of the same address space. The concept of Harvard versus Von Neumann architectures is however distinct from whether there are separate program and data memory buses. For example, the INTEL 8051 is a Harvard architecture which has the same bus for both; it just runs slower as a result of not being able to access both memory regions simultaneously as compared with a separate-bus Harvard architecture.
The prior art also contains examples (e.g. the INTEL 8085) in which chip pin count is reduced by timesharing at least some of the pins for both data and address lines. The cited 8085 microprocessor has a 16-bit address bus whose least significant 8 bits are also time multiplexed for use as the data bus. In this case, the CPU operates by applying a 16-bit address to the bus while generating a signal called Address Latch Enable (ALE) and then removing the address from the least significant 8-bit lines while outputting a Read or Write control signal to the memory and re-using the 8 lines for an 8-bit byte data transfer. Nonetheless, the sixteen address lines are in one-for-one correspondence with the sixteen bits required for addressing the entire address space.